At present, there are two representation forms for a computational task: on a general purpose processor (GPP), the task is generally presented in a form of software code, which is referred to as a software task; while on an application-specific integrated circuit, the task is generally presented in a form of an application-specific hardware circuit, which is referred to as a hardware task. The software task has advantages of good flexibility and being easy to modify and debug, and has a disadvantage of unsatisfactory computation speed; while the hardware task has an advantage of high speed, and has disadvantages of being less flexible and not easy to debug. A heterogeneous multi-core reconfigurable computing platform is an effective means to balance a general purpose processor and an application-specific integrated circuit. The heterogeneous multi-core reconfigurable computing platform not only can achieve a quite high speedup ratio by using a reconfigurable logic component, but also can have good flexibility by using a reconfigurable technology or adding a general purpose processor. In addition, the heterogeneous multi-core reconfigurable computing platform can overcome deficiencies, such as high costs of the application-specific integrated circuit caused due to a complex design and manufacturing process at an early stage and non-reusability.
Reconfigurable resources (namely, hardware logical resources) on the heterogeneous multi-core reconfigurable computing platform are usually quite limited, and it is required to perform reconfiguration on the reconfigurable resources, so as to implement hardware execution of a task. Hardware resource reconfiguration on the heterogeneous multi-core reconfigurable computing platform can be classified into static reconfiguration and dynamic reconfiguration. Static reconfiguration refers to static reconfiguration of hardware logical resources of a system. That is, online programming is performed in various manners during an idle period of the system, so as to perform configuration of logical functions of a reconfigurable hardware logic component. Dynamic reconfiguration refers to performing dynamic configuration of logical functions of a reconfigurable logic component in real time during a real-time operating period of a system. For example, re-configuration can be performed only on a logical unit (namely, a reconfigurable resource) that needs to be modified in the system, which does not affect normal operation of an unmodified logical unit. Relative to the static reconfiguration, the dynamic reconfiguration shortens reconfiguration time, which on the one hand reduces overheads of the system, and on the other hand improves the operating efficiency of the system. To improve resource usage, in the prior art, a heterogeneous multi-core reconfigurable computing platform generally uses dynamic reconfiguration.
At present, a heterogeneous multi-core reconfigurable computing platform generally uses a Window-based method for task migration to perform reconfiguration. A window is defined as a time interval between current reconfiguration and next reconfirmation. A window includes three phases: a Hardware Execution time, a Scheduling time, and a Reconfiguration time, where the scheduling time is hidden in the hardware execution time. In the prior art, a size of a reconfiguration window is fixed, and the size of the window affects system performance. For example, an excessively large window causes a reconfigurable resource to be in an idle state for a long period of time, which lowers resource usage and system performance. An excessively small window causes excessively frequent system reconfiguration, thereby introducing extra reconfiguration overheads and lowering system performance.